1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a semiconductor apparatus capable of performing a read-while-write operation.
2. Related Art
According to the demand for low power consumption of a semiconductor apparatus which is one of elements forming a semiconductor system, research has been conducted on next-generation memory apparatuses which are nonvolatile and do not require a refresh operation. A phase-change random access memory (PRAM) which is one of the next-generation memory apparatuses generates a phase change between amorphous and crystalline structures of a phase change layer formed of chalcogenide through Joule heating caused by a current between a top electrode and a heating electrode serving as a heater, and writes or erases data using a resistance difference occurring at this time.
FIG. 1 illustrates a bank structure of a conventional PRAM. FIG. 2 illustrates a chip structure of the conventional PRAM.
Referring to FIG. 1, a bank 100 of the conventional PRAM includes a plurality of cell mats 110, an X-decoder 120, a Y-decoder 130, a write driver (W/D) & sense amplifier (S/A) block 140, a global bit line switch (GYSW) 150, a local bit line switch (LYSW) 160, a local word line switch (LXSW) 170, and an XY control block 180 configured to control operations of the X-decoder 120 and the Y-decoder 130. FIG. 1 also illustrates bit lines BL, global bit lines GBL, and word lines WL.
Referring to FIG. 2, the bank 100 of the conventional PRAM is arranged in a core area 210, and a write/read operation controller 221 to control read and write operations of the respective banks 100 (i.e., Bank 0 to Bank 7) is arranged in a peripheral area 220.
The conventional PRAM configured in such a manner generally exhibits low data processing speed. Therefore, a read-while-write operation is required to increase the data processing speed. Accordingly, in order to enable the read-while-write operation, the conventional PRAM is configured to guarantee independent operations of two or more banks such that, when any one bank performs a read operation, another bank performs a write and verify operation.
As illustrated in FIG. 2, however, each of the banks 100 of the conventional PRAM includes the X-decoder 120, the Y-decoder 130, and the W/D & S/A block 140 so as to independently perform an operation. Therefore, according to the number of banks 100, the area of the PRAM is inevitably increased by the components included in the respective banks 100.